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CY2077
High-accuracy EPROM Programmable Single-PLL Clock Generator
Features * High-accuracy PLL with 12-bit multiplier and 10-bit divider * EPROM-programmability * 3.3V or 5V operation * Operating frequency -- 390 kHz-133 MHz at 5V -- 390 kHz-100 MHz at 3.3V * Reference input from either a 10-30 MHz fundamental toned crystal or a 1-75 MHz external clock * * * Benefits Enables synthesis of highly accurate and stable output clock frequencies with zero PPM Enables quick turnaround of custom frequencies Supports industry standard design platforms Services most PC, networking, and consumer applications
* * * *
Lowers cost of oscillator as PLL can be programmed to a high frequency using either a low-frequency, low-cost crystal, or an existing system clock EPROM-selectable TTL or CMOS duty-cycle levels Duty cycle centered at 1.5V or VDD/2 Provides flexibility to service most TTL or CMOS applications Sixteen selectable post-divide options, using either PLL Provides flexibility in output configurations and testing or reference oscillator/external clock Programmable PWR_DWN or OE pin, with Enables low-power operation or output enable function and asynchronous or synchronous modes flexibility for system applications, through selectable instantaneous or synchronous change in outputs Low jitter outputs typically Suitable for most PC, consumer, and networking applications -- 80 ps at 3.3V/5V Controlled rise and fall times and output slew rate Has lower EMI than oscillators Available in both commercial and industrial Suitable to fit most applications temperature ranges Factory-programmable device options Easy customization and fast turnaround Logic Block Diagram Pin Configuration
PWR_DWN or OE Phase Detector Crystal Oscillator Charge Pump Configuration EPROM VDD XTALOUT XTALIN PD/OE 8-pin Top View 1 2 3 4 8 7 6 5 CLKOUT VSS VSS VSS
XTALOUT[1] XTALIN or external clock
Q 10 bits
VCO P 12 bits
HIGH ACCURACY PLL
MUX
/ 1, 2, 4, 8, 16, 32, 64, 128
Note: 1. When using an external clock source, leave XTALOUT floating.
CLKOUT
Cypress Semiconductor Corporation Document #: 38-07210 Rev. *B
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 07, 2002
CY2077
Functional Description
The CY2077 is an EPROM-programmable, high-accuracy, general-purpose, PLL-based design for use in applications such as modems, disk drives, CD-ROM drives, video CD players, DVD players, games, set-top boxes, and data/telecommunications. The CY2077 can generate a clock output up to 133 MHz at 5V or 100 MHz at 3.3V. It has been designed to give the customer a very accurate and stable clock frequency with little to zero PPM error. The CY2077 contains a 12-bit feedback counter divider and 10-bit reference counter divider to obtain a very high resolution to meet the needs of stringent design specifications. Furthermore, there are eight output divide options of /1, /2, /4, /8, /16, /32, /64, and /128. The output divider can select between the PLL and crystal oscillator output/external clock, providing a total of 16 different options to add more flexibility in designs. TTL or CMOS duty cycles can be selected. Power management with the CY2077 is also very flexible. The user may choose either a PWR_DWN or an OE feature with which both have integrated pull-up resistors. PWR_DWN and OE signals can be programmed to have asynchronous and synchronous timing with respect to the output signal. There is a weak pull-down on the output that will pull CLKOUT LOW when either the PWR_DWN or OE signal is active. This weak pull-down can easily be overridden by another clock signal in designs where multiple clock signals share a signal path. Multiple options for output selection, better power distribution layout, and controlled rise and fall times enable the CY2077 to be used in applications that require low jitter and accurate reference frequencies.
PLL Output Frequency
The CY2077 contains a high-resolution PLL with 12-bit multiplier and 10-bit divider.[2] The output frequency of the PLL is determined by the following formula: 2 * (P + 5) F PLL = --------------------------- * FREF (Q + 2) where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values. The calculation of P and Q values for a given PLL output frequency is handled by the CyClocks software. Refer to the "Custom Configuration Request Procedure" section for details.
Power Management Features
PWR_DWN and OE options are configurable by EPROM programming for the CY2077. In PWR_DWN mode, all active circuits are powered down when the control pin is set LOW. When the control pin is set back HIGH, both the PLL and oscillator circuit must re-lock. In the case of OE, the output is three-stated and weakly pulled down when the control pin is set LOW. The oscillator and PLL are still active in this state, which leads to a quick clock output return when the control pin is set back HIGH. Additionally, PWR_DWN and OE can be configured to occur asynchronously or synchronously with respect to CLKOUT. In asynchronous mode, PWR_DWN or OE disables CLKOUT immediately (allowing for logic delays), without respect to the current state of CLKOUT. Synchronous mode will prevent output glitches by waiting for the next falling edge of CLKOUT after PWR_DWN or OE becomes asserted. In either asynchronous or synchronous setting, the output is always enabled synchronously by waiting for the next falling edge of CLKOUT.
EPROM Configuration Block
Table 1 summarizes the features configurable by EPROM. Table 1. EPROM Adjustable Features EPROM Adjustable Features Feedback counter value (P) Reference counter value (Q) Output divider selection Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous) Adjust Freq.
Pin Summary
Pin Name VDD VSS XD XG PWR_DWN / OE CLKOUT Pin # 1 5,6,7 2 3 4 8 Pin Description Voltage supply. Ground (all the pins have to be grounded). Crystal output (leave this pin floating when external reference is used). Crystal input or external input reference. EPROM programmable power-down or output enable pin. Weak pull-up. Clock output. Weak pull-down.
Note: 2. When using CyClocks, please note that the PLL frequency range is from 50 MHz to 250 MHz for 5V VDD supply, and 50 MHz to 180 MHz for 3V VDD supply. The output frequency is determined by the selected output divider.
Document #: 38-07210 Rev. *B
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CY2077
Device Functionality: Output Frequencies
Symbol Fo Description Output frequency Condition VDD = 4.5-5.5V VDD = 3.0-3.6V Min. 0.39 0.39 Max. 133 100 Unit MHz MHz
Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V
Input Voltage........................................... -0.5V to VDD +0.5V Storage Temperature (Non-Condensing).... -55C to +150C Junction Temperature ................................................. 150C Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015)
Operating Conditions for Commercial Temperature Device
Parameter VDD TA CTTL Description Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on outputs for TTL levels VDD = 4.5 - 5.5V, Output frequency = 1 - 40 MHz VDD = 4.5 - 5.5V, Output frequency = 40 - 125 MHz VDD = 4.5 - 5.5V, Output frequency = 125 - 133 MHz Max. Capacitive Load on outputs for CMOS levels VDD = 4.5 - 5.5V, Output frequency = 1 - 40 MHz VDD = 4.5 - 5.5V, Output frequency = 40 - 125 MHz VDD = 4.5 - 5.5V, Output frequency = 125 - 133 MHz VDD = 3.0 - 3.6V, Output frequency = 1 - 40 MHz VDD = 3.0 - 3.6V, Output frequency = 40 - 100 MHz Reference Frequency, input crystal with Cload = 10 pF Reference Frequency, external clock source Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Min. 3.0 0 Max. 5.5 +70 50 25 15 50 25 15 30 15 30 75 50 Unit V C pF pF pF pF pF pF pF pF MHz MHz ms
CCMOS
XREF
10 1 0.05
tPU
Electrical Characteristics TA = 0C to +70C
Parameter Description VIL VIH VOL VOHCMOS VOHTTL IIL IIH IDD IDDS[3] RUP Low-level Input Voltage High-level Input Voltage Low-level Output Voltage Test Conditions VDD = 4.5 - 5.5V VDD = 3.0 - 3.6V VDD = 4.5 - 5.5V VDD = 3.0 - 3.6V VDD = 4.5 - 5.5V, IOL= 16 mA VDD = 3.0 - 3.6V, IOL= 8 mA VDD - 0.4 VDD - 0.4 2.4 10 5 45 25 25 10 1.1 50 3.0 100 20 100 50 8.0 200 2.0 0.7VDD 0.4 0.4 Min. Typ. Max. 0.8 0.2VDD Unit V V V V V V V V V A A mA mA A M k A
High-level Output Voltage, VDD = 4.5 - 5.5V, IOH= -16 mA CMOS levels VDD = 3.0 - 3.6V, IOH= -8 mA High-level Output Voltage, VDD = 4.5 - 5.5V, IOH= -8 mA TTL levels Input Low Current Input High Current Power Supply Current, Unloaded Stand-by current (PD = 0) Input Pull-Up Resistor VIN = 0V VIN = VDD VDD = 4.5 - 5.5V, Output frequency <= 133 MHz VDD = 3.0 - 3.6V, Output frequency <= 100 MHz VDD = 4.5 - 5.5V VDD = 3.0 - 3.6V VDD = 4.5 - 5.5V, VIN = 0V VDD = 4.5 - 5.5V, VIN = 0.7VDD
IOE_CLKOUT CLKOUT Pulldown current VDD = 5.0 Note: 3. If external reference is used, it is required to stop the reference (set reference to LOW) during power down.
Document #: 38-07210 Rev. *B
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CY2077
Output Clock Switching Characteristics Commercial Over the Operating Range[4]
Parameter t1w Description Test Conditions Min. Typ. Max. Unit 45 45 45 45 45 45 45 40 55 55 55 55 55 55 55 60 1.8 1.2 0.9 3.4 4.0 2.4 1.8 1.2 0.9 3.4 4.0 2.4 1 T/2 10 1 T/2 10 T 2 T+ 10 15 2 T+ 10 15 1.5T + 25ns % % % % % % % % ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ms ns ns ns Output Duty Cycle at 1.4V, 1 - 40 MHz, CL <= 50 pF VDD = 4.5 - 5.5V 40 - 125 MHz, CL <= 25 pF t1w = t1A / t1B 125 - 133 MHz, CL <= 15 pF Output Duty Cycle at VDD/2, VDD = 4.5 - 5.5V t1x = t1A / t1B Output Duty Cycle at VDD/2, VDD = 3.0 - 3.6V t1y = t1A / t1B Output Clock Rise Time 1 - 40 MHz, CL <= 50 pF 40 - 125 MHz, CL <= 25 pF 125 - 133 MHz, CL <= 15 pF 1 - 40 MHz, CL <= 30 pF 40 - 100 MHz, CL <= 15 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 50 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 25 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 15 pF Between 0.2VDD - 0.8VDD, VDD= 4.5V - 5.5V, CL = 50 pF Between 0.2VDD - 0.8VDD, VDD= 3.0V - 3.6V, CL = 30 pF Between 0.2VDD - 0.8VDD, VDD= 3.0V - 3.6V, CL = 15 pF Between 0.8V -2.0V, VDD = 4.5V - 5.5V, CL = 50 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 25 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 15 pF Between 0.2VDD - 0.8VDD, VDD= 4.5V - 5.5V, CL = 50 pF Between 0.2VDD - 0.8VDD, VDD= 3.0V - 3.6V, CL = 30 pF Between 0.2VDD - 0.8VDD, VDD= 3.0V - 3.6V, CL = 15 pF PWR_DWN pin LOW to HIGH[5] PWR_DWN pin LOW to output LOW (T= period of output CLK) PWR_DWN pin LOW to output LOW From power-on[5] OE pin LOW to output high-Z (T= period of output CLK) OE pin LOW to output high-Z OE pin LOW to HIGH (T= period of output CLK) VDD = 3.0V - 3.6V, 4.5V - 5.5V, Fo > 33 MHz, VCO > 100 MHz VDD = 3.0V - 5.5V, Fo < 33 MHz
t1x
t1y
t2
t3
Output Clock Fall Time
t4 t5a t5b t6 t7a t7b t8
Start-Up Time Out of Power-down Power-down Delay Time (synchronous setting) Power-down Delay Time (asynchronous setting) Power-up Time Output Disable Time (synchronous setting) Output Disable Time (asynchronous setting) Output Enable Time (always synchronous enable) Peak-to-Peak Period Jitter
t9
80 150 0.3% 1%
ps % of FO
Notes: 4. Not all parameters measured in production testing. 5. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70.
Document #: 38-07210 Rev. *B
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CY2077
Operating Conditions for Industrial Temperature Device
Parameter VDD TA CTTL Supply Voltage Operating Temperature, Ambient Max. Capacitive Load on outputs for TTL levels VDD = 4.5 - 5.5V, Output frequency = 1 - 40 MHz VDD = 4.5 - 5.5V, Output frequency = 40 - 125 MHz VDD = 4.5 - 5.5V, Output frequency = 125 - 133 MHz Max. Capacitive Load on outputs for CMOS levels VDD = 4.5 - 5.5V, Output frequency = 1 - 40 MHz VDD = 4.5 - 5.5V, Output frequency = 40 - 125 MHz VDD = 4.5 - 5.5V, Output frequency = 125 - 133 MHz VDD = 3.0 - 3.6V, Output frequency = 1 - 40 MHz VDD = 3.0 - 3.6V, Output frequency = 40 - 100 MHz Reference Frequency, input crystal with Cload = 10 pF Reference Frequency, external clock source tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 10 1 0.05 Description Min. 3.0 -40 Max. 5.5 +85 35 15 10 35 15 10 20 10 30 75 50 Unit V C pF pF pF pF pF pF pF pF MHz MHz ms
CCMOS
XREF
Electrical Characteristics TA = -40C to +85C
Parameter Description VIL VIH VOL VOHCMOS VOHTTL IIL IIH IDD IDDS[3] RUP Low-level Input Voltage High-level Input Voltage Low-level Output Voltage High-level Output Voltage, CMOS levels High-level Output Voltage, TTL levels Input Low Current Input High Current Power Supply Current, Unloaded Stand-by current (PD = 0) Input Pull-Up Resistor Test Conditions VDD = 4.5 - 5.5V VDD = 3.0 - 3.6V VDD = 4.5 - 5.5V VDD = 3.0 - 3.6V VDD = 4.5 - 5.5V, IOL= 16 mA VDD = 3.0 - 3.6V, IOL= 8 mA VDD = 4.5 - 5.5V, IOH= -16 mA VDD = 3.0 - 3.6V, IOH= -8 mA VDD = 4.5 - 5.5V, IOH= -8 mA VIN = 0V VIN = VDD VDD = 4.5 - 5.5V, Output frequency <= 133 MHz VDD = 3.0 - 3.6V, Output frequency <= 100 MHz VDD = 4.5 - 5.5V VDD = 3.0 - 3.6V VDD = 4.5 - 5.5V, VIN = 0V VDD = 4.5 - 5.5V, VIN = 0.7VDD 1.1 50 25 10 3.0 100 20 VDD - 0.4 VDD - 0.4 2.4 10 5 45 25 100 50 8.0 200 2.0 0.7VDD 0.4 0.4 Min. Typ. Max. 0.8 0.2VDD Unit V V V V V V V V V A A mA mA A M k A
IOE_CLKOUT CLKOUT Pull-down current VDD = 5.0
Output Clock Switching Characteristics Industrial Over the Operating Range[4]
Parameter t1w Description Output Duty Cycle at 1.4V, VDD = 4.5 - 5.5V t1w = t1A / t1B Test Conditions 1 - 40 MHz, CL <= 35 pF 40 - 125 MHz, CL <= 15 pF 125 - 133 MHz, CL <= 10 pF Min. Typ. 45 45 45 45 45 45 45 40 Max. Unit 55 55 55 55 55 55 55 60 % % % % % % % %
t1x
Output Duty Cycle at 1 - 40 MHz, CL <= 35 pF VDD/2, VDD = 4.5 - 5.5V 40 - 125 MHz, CL <= 15 pF t1x = t1A / t1B 125 - 133 MHz, CL <= 10 pF Output Duty Cycle at 1- 40 MHz, CL <= 20 pF VDD/2, VDD = 3.0 - 3.6V 40 - 100 MHz, CL <= 10 pF t1y = t1A / t1B
t1y
Document #: 38-07210 Rev. *B
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CY2077
Output Clock Switching Characteristics Industrial Over the Operating Range[4]
Parameter t2 Description Test Conditions Min. Typ. Max. Unit 1.8 1.2 0.9 3.4 4.0 2.4 1.8 1.2 0.9 3.4 4.0 2.4 1 T/2 10 1 T/2 10 T 2 T+10 15 2 ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ms Output Clock Rise Time Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 35 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 15 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 10 pF Between 0.2VDD - 0.8VDD, VDD= 4.5V - 5.5V, CL = 35 pF Between 0.2VDD - 0.8VDD, VDD= 3.0V - 3.6V, CL = 20 pF Between 0.2VDD - 0.8VDD, VDD= 3.0V - 3.6V, CL = 10 pF Output Clock Fall Time Between 0.8V - 2.0V, VDD = 4.5V - 5.5V, CL = 35 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 15 pF Between 0.8 - 2.0V, VDD = 4.5V - 5.5V, CL = 10 pF Between 0.2VDD - 0.8VDD, VDD= 4.5V - 5.5V, CL = 35 pF Between 0.2VDD - 0.8VDD, VDD= 3.0V - 3.6V, CL = 20 pF Between 0.2VDD - 0.8VDD, VDD= 3.0V - 3.6V, CL = 10 pF PWR_DWN pin LOW to HIGH[5]
t3
t4 t5a t5b t6 t7a t7b t8
Start-up Time Out of Power-down
Power-down Delay Time PWR_DWN pin LOW to output LOW (synchronous setting) (T= period of output clk) Power-down Delay Time PWR_DWN pin LOW to output LOW (asynchronous setting) Power-up Time Output Disable Time (synchronous setting) Output Disable Time (asynchronous setting) Output Enable Time (always synchronous enable) Peak-to-Peak Period Jitter From power on[5] OE pin LOW to output high-Z (T= period of output clk) OE pin LOW to output high-Z OE pin LOW to HIGH (T = period of output clk) VDD = 3.0V - 3.6V, 4.5V - 5.5V, Fo > 33 MHz, VCO > 100 MHz VDD = 3.0V - 5.5V, Fo < 33 MHz
T + 10 ns 15 1.5T + 25ns 150 1% ns ns
t9
80 0.3%
ps % of FO
Switching Waveforms
Duty Cycle Timing (t1w, t1x, t1y) OUTPUT t1A t1B
Output Rise/Fall Time OUTPUT t2 t3 VDD 0V
Document #: 38-07210 Rev. *B
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CY2077
Switching Waveforms (continued)
Power-down Timing (synchronous and asynchronous modes) VDD VIH POWER DOWN VIL 0V
(synchronous[6])
t4
CLKOUT T t5a 1/f
(asynchronous[7])
CLKOUT t5b 1/f
Power-up Timing VDD POWER UP CLKOUT Output Enable Timing (synchronous and asynchronous modes) VDD OUTPUT ENABLE VIL 0V T CLKOUT
(synchronous[6])
VDD - 10% t6 min 30 s max 30 ms 1/f
0V
VIH
High Impedance t7a t8 High Impedance t7b t8
CLKOUT
(asynchronous[7])
Notes: 6. In synchronous mode the power-down or output three-state is not initiated until the next falling edge of the output clock. 7. In asynchronous mode the power-down or output three-state occurs within 25 ns regardless of position in the output clock cycle.
Document #: 38-07210 Rev. *B
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CY2077
Typical Rise Time[8] and Fall Time[8] Trends for CY2077
Rise/Fall Time vs. VDD over Temperatures
Rise Time vs. VDD -- CMOS duty Cycle Cload = 15pF 2.00 Rise Time (ns) 1.80 1.60 1.40 1.20 1.00 2.7 3.0 3.3 VDD (V) 3.6 3.9 -40C 25C 85C
Fall Time vs. VDD -- CMOS duty Cycle Cload = 15pF 2.00 1.80 1.60 1.40 1.20 1.00 2.7 3.0 3.3 VDD (V) 3.6 3.9 Fall Time (ns)
-40C 25C 85C
Rise Time vs. VDD -- TTL duty Cycle Cload = 15pF Rise Time (ns) 0.70 0.60 0.50 0.40 0.30 0.20 4.0 4.5 5.0 VDD (V) 5.5 6.0 0.70 0.60 0.50 0.40 0.30 0.20 Fall Time (ns)
Fall Time vs. VDD -- TTL duty Cycle Cload = 15pF
-40C 25C 85C
-40C 25C 85C 4.0 4.5 5.0 VDD (V) 5.5 6.0
Rise/Fall Time vs. Output Loads over Temperatures
Rise Time vs. CLoad over Temperature VDD = 3.3v, CMOS output Rise Time (ns)
Fall Time vs. CLoad over Temperature VDD = 3.3v, CMOS output Fall Time (ns) 2.00 1.50 1.00 10 15 20 25 30 35 Cload (pF) -40C 25C 85C
2.50 2.00 1.50 1.00 10 15 20 25 30 35 Cload (pF) -40C 25C 85C
Note: 8. Rise/Fall Time for CMOS output is measured between 1.2 VDD and 0.8 VDD. Rise/Fall Time for TTL output is measured between 0.8V and 2.0V.
Document #: 38-07210 Rev. *B
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CY2077
Typical Duty Cycle[9] Trends for CY2077 Duty Cycle vs. VDD over Temperatures
Duty Cycle vs. VDD over Temperature (TTL Duty Cycle Output, Fout=50MHz, Cload = 50pF) Duty Cycle (%) 55.00 53.00 51.00 49.00 47.00 45.00 4.0 4.5 5.0 VDD (V) 5.5 6.0 Duty Cycle (%) Duty Cycle vs. VDD over Temperature (CMOS Duty Cycle Ouput, Fout=50MHz, Cload=50pF) 55.00 53.00 51.00 49.00 47.00 45.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (v)
-40C 25C 85C
-40C 25C 85C
Duty Cycle vs. Output Load
Duty Cycle vs. CLoad with Various VDD (Fout = 50MHz, Temp = 25C) Duty Cycle (%) 55.00 53.00 51.00 49.00 47.00 45.00 10 15 20 25 30 35 40 45 50 55 Cload (pF)
VDD=4.5V VDD=5.0V VDD=5.5V
Duty Cycle vs. Output Frequency over Temperatures
Output Duty Cycle vs. Fout over Temperature (Vdd = 5V, Cload = 15pF) 55.00% 54.00% 53.00% 25C 52.00% 85C 51.00% -40C 50.00% 20 30 40 50 60 70 80 Output Frequency (MHz)
Note: 9. Duty cycle is measured at 1.4V for TTL output and 0.5 VDD for CMOS output.
Document #: 38-07210 Rev. *B
Output DC (%)
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CY2077
Typical Jitter Trends for CY2077 Period Jitter (pk-pk) vs. VDD over Temperatures
Period Jitter (pk-pk) vs. VDD over Temperatures (Fout=40MHz, Cload = 30pF) 100 Period JItter (ps) 80 60 40 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) -40C 25C 85C
Period Jitter (pk-pk) vs. Output Frequency over Temperatures
Output Jitter (pk-pk) vs. Output Frequency (VDD=3.3V, Cload=15pf, CMOS output)
1 00 80
Jitter (ps)
60 40 20 0 0 20 40 60 80 100 1 20 140
25C -40C 85C
Output frequency (MHz)
Output Jitter(pk-pk) vs. Output Frequency (VDD=5.0V, Cload=15pf, CMOS output)
1 00 80
Jitter (ps)
60 40 20 0 0 20 40 60 80 1 00 1 20 1 40
25C -40C 85C
Output frequency (MHz)
Custom Configuration Request Procedure
The CY2077 is an EPROM-programmable device that is configured in the factory. The output frequencies requested will be matched as closely as the internal PLL divider and multiplier options allow. All custom requests must be submitted to your local Cypress Field Application Engineer (FAE) or sales representative. The method used to request custom configurations is: Use CyClocks software of version 3.65 or greater. This software automatically calculates the output frequencies that can be generated by the CY2077 devices and Document #: 38-07210 Rev. *B
provides a print-out of final pinout which can be submitted (in electronic or print format) to your local FAE or sales representative. The CyClocks software is available free of charge from the Cypress website (http://www.cypress.com) or from your local sales representative. Once the custom request has been processed you will receive a part number with a three-digit extension (e.g., CY2077SC-103) specific to the frequencies and pinout of your device. This will be the part number used for samples requests and production orders.
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CY2077
Ordering Information
Order Code[10, 11] CY2077SC-xxx CY2077SC-xxxT CY2077SI-xxx CY2077SI-xxxT CY2077ZC-xxx CY2077ZC-xxxT CY2077ZI-xxx CY2077ZI-xxxT CY2077FS CY2077FSI CY2077FZ CY2077FZI Package Name S8 S8 S8 S8 Z8 Z8 Z8 Z8 S8 S8 Z8 Z8 Package Type 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin SOIC 8-pin SOIC-Tape & Reel 8-pin TSSOP 8-pin TSSOP-Tape & Reel 8-pin TSSOP 8-pin TSSOP-Tape & Reel 8-pin SOIC 8-pin SOIC 8-pin TSSOP 8-pin TSSOP Operating Temp. Range Commercial (T = 0C to 70C) Commercial (T = 0C to 70C) Industrial (T = -40C to 85C Industrial (T = -40C to 85C Commercial (T = 0C to 70C) Commercial (T = 0C to 70C) Industrial (T = -40C to 85C Industrial (T = -40C to 85C Commercial (T = 0C to 70C) Industrial (T = -40C to 85C) Commercial (T = 0C to 70C) Industrial (T = -40C to 85C Operating Voltage 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V 3.3V or 5V
Package Diagrams
8-pin (150-mil) SOIC S8
51-85066-A
Notes: 10. The CY2077SC-xxx(T), CY2077SI-xxx(T), CY2077ZC-xxx(T), and CY2077ZI-xxx(T) are factory programmed configurations. Factory programming is available for high-volume design opportunities of 100Ku/year or more in production. For more details, contact your local Cypress FAE or Cypress Sales Representative. 11. The CY2077F are field programmable. For more details, contact you local Cypress FAE or Cypress Sales Representative.
Document #: 38-07210 Rev. *B
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CY2077
Package Diagrams (continued)
8-pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
51-85093
CyClocks is a trademark of Cypress Semiconductor. All product or company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07210 Rev. *B
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2077
Document Title: CY2077 High-accuracy EPROM Programmable Single-PLL Clock Generator Document Number: 38-07210 REV. ** *A *B ECN NO. 111727 114938 121843 Issue Date 02/07/02 07/24/02 12/14/02 Orig. of Change DSG CKN RBI Description of Change Convert from Spec number: 38-01009 to 38-07210 Added table and notes to page 11 Power up requirements added to Operating Conditions Information
Document #: 38-07210 Rev. *B
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